ds706 (v1.1) february 2, 2011 www.xilinx.com product specification 1 ? copyright 2008?2011 xilinx, inc. xilinx, the xilinx logo, virt ex, spartan, ise, and other designated brands included herein a re trademarks of xilinx in the united states and other countries. pci, pci express, pcie, and pci-x are trademarks of pci-sig. all other trademarks are the property of their res pective owners. general description the extended spartan?-3a family of field-programmable gate arrays (fpgas) solves the design challenges in many high- volume, cost-sensitive electronic applications. with 12 devices ranging from 50 ,000 to 3.4 million syst em gates (as shown in ta bl e 1 ), the extended spartan-3a family provides a broad range of densities and package options, integrated dsp macs, and low total system cost while increasing functionality. the extended spartan-3a family includes the spartan-3a devices and the higher density spartan-3a dsp devices. it also in cludes the nonvolatile spartan-3an devices, which combine leading-edge fpga and flash technologies to provide a new evol ution in security, protection and functionality, ideal for space-critical or se cure applications. the extended spartan-3a family improves system performance and reduces the cost of configuration. these enhancements, combined with proven 90 nm process technology, deliver more functionality and bandwidth per dollar. because of its exceptionally low cost, the extended spartan-3a family is ideally suited to a wide range of consumer electronics applications, including broadband access, home netwo rking, display/projection, and digital television equipment. the extended spartan-3a family is a superior alternative to mask-programmed asics. fpgas avoid the high initial cost, lengthy development cycles, the inheren t inflexibility of conventional asics, and permit field design upgrades. summary of extended spartan-3a family features ? very low-cost, high-performance logic solution for high- volume, cost-conscious applications ? low-cost qfp and bga packaging, pb-free options ? flexible power management ? leading connectivity platform ? abundant, flexible logic resources ? dedicated resources for high-speed digital signal processing applications ? precise clock management with up to eight digital clock managers (dcms) ? integrated flash memory in spartan-3an devices ? eight low-skew global clock networks, eight additional clocks per half device, plus abundant low-skew routing ? hierarchical selectram? memory architecture ? configuration interface to industry-standard proms ? complete xilinx? ise? and free webpack? development system software support ? microblaze? and picoblaze? embedded processors reduce risk ? low-cost starter kits from x ilinx, distributors, and third parties ? xa versions available for automotive applications 7 extended spartan-3a family overview ds706 (v1.1) february 2, 2011 product specification r table 1: summary of extend ed spartan-3a family attributes device system gates equivalent logic cells clbs slices distributed ram bits ( 1 ) block ram bits ( 1 ) in-system flash bits ( 2 ) dedicated multipliers dsp48as dcms maximum user i/o xc3s50a/an 50k 1,584 176 704 11k 54k 1m 3 - 2 144 xc3s200a/an 200k 4,032 448 1,792 28k 288k 4m 16 - 4 248 ( 3 ) xc3s400a/an 400k 8,064 896 3,584 56k 360k 4m 20 - 4 311 xc3s700a/an 700k 13,248 1,472 5,888 92k 360k 8m 20 - 8 372 xc3s1400a/an 1400k 25,344 2,816 11,264 176k 576k 16m 32 - 8 502 xc3sd1800a 1800k 37,440 4,160 16,640 260k 1,512k - - 84 8 519 XC3SD3400A 3400k 53,712 5,968 23,872 373k 2,268k - - 126 8 469 notes: 1. by convention, one kb is equivalent to 1,024 bits. 2. in-system flash is available in the spartan-3an devices only. 3. maximum user i/o for xc3s200an is 195.
extended spartan-3a family overview ds706 (v1.1) february 2, 2011 www.xilinx.com product specification 2 r extended spartan-3a family features this section describes the features of the extended spartan-3a family of fpgas. ? very low-cost, high-performance logic solution for high- volume, cost-conscious applications ? use fewer standard components ? increase system reliability ? flexible power management ? low 1.2v core voltage ? selectable i/o voltage with 3.3v, 2.5v, 1.8v, 1.5v, and 1.2v signaling ? full 3.3v 10% comp atibility and hot swap compliance ? dual-range auxiliary voltage allows 3.3v setting to simplify 3.3v-only design ? suspend and hibernate modes reduce system power ? leading connectivity platform ? multi-standard selectio? interface pins support most popular and emerging signaling standards ? up to 519 i/o pins or 227 differential signal pairs ? lvcmos, lvttl, hstl, sstl single-ended i/o ? selectable output drive, up to 24 ma per pin ? quietio standard reduces i/o switching noise ? 640+ mb/s data transfer rate per differential i/o ? lvds, rsds, mini-lvds, hstl/sstl differential i/o with integrated differential termination resistors ? enhanced double data rate (ddr) support ? compliant to 32-/64-bit, 33/66 mhz pci? technology ? abundant, flexible logic resources ? densities up to 53,712 logic cells, including optional shift register or distributed ram support ? efficient wide multiplexe rs and wide logic improve performance and density ? fast look-ahead carry logic ? ieee 1149.1/1532 jtag programming/debug port ? dedicated resources for high-speed digital signal processing applications ? 18-bit by 18-bit multiplier with optional pipeline ? 250 mhz xtremedsp? dsp48a block in the largest two devices - 48-bit accumulator for multiply-accumulate (mac) operation - integrated 18-bit pre-adder for multiply or multiply-add operation - optional cascaded multiply or mac - fills the dsp performa nce gap between dsp processors and high-end custom solutions ? precise clock management with up to eight digital clock managers (dcms) ? clock skew elimination (delay locked loop) ? frequency synthesis, multiplication, division ? high-resolution phase shifting ? wide frequency range (5 mhz to over 320 mhz) ? integrated flash memory in spartan-3an devices ? up to 16 mb of internal flash for configuration and application storage ? up to 11 mb of user storage available for embedded processing, code shadowing, or scratchpad memory ? enables single-chip board designs for space- conscious applications ? enhanced design security with flash memory protection and security register ? eight low-skew global clock networks, eight additional clocks per half device, plus abundant low-skew routing ? hierarchical selectram memory architecture ? up to 2.2 mb of fast block ram with byte write enables for processor applications ? up to 373 kb of efficient distributed ram ? external ddr/ddr2 sdram support up to 400 mb/s ? configuration interface to industry-standard proms ? low-cost, space-saving spi serial flash prom ? x8 or x8/x16 parallel nor flash prom ? low-cost xilinx platform flash with jtag ? load multiple bitstreams under fpga control with multiboot capability ? complete xilinx ise and free webpack development system software support ? industry?s most comprehensive ip library ? microblaze and picoblaze embedded processors ? integrate soft processor into fpga to reduce bill of materials ? reduce obsolescence risks with soft processors ? low-cost qfp and bga packaging, pb-free options ? common footprints support easy density migration ? low-cost starter kits from x ilinx, distributors, and third parties ? complete starter kits designed for cost-sensitive, high-volume applications with design examples ? xa versions available for automotive applications
extended spartan-3a family overview ds706 (v1.1) february 2, 2011 www.xilinx.com product specification 3 r architectural overview the extended spartan-3a family architecture consists of five fundamental programmable functional elements: ? configurable logic blocks (clbs) contain flexible look-up tables (luts) that implement logic plus storage elements used as flip-flops or latches. clbs perform a wide variety of logical functions as well as store data. ? input/output blocks (iobs) control the flow of data between the i/o pins and the internal logic of the device. iobs support bidirectional data flow plus 3-state operation. supports a variety of signal standards, including several high-performance differential standards. double data-rate (ddr) registers are included. ? block ram provides data storage in the form of 18-kbit dual-port blocks. ? multiplier or dsp48a blocks accept two 18-bit binary numbers as inputs and calculate the product. the dsp48a blocks in the two largest members of the extended spartan-3a family add an 18-bit pre-adder and 48-bit accumulator. ? digital clock manager (dcm) blocks provide self- calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. configuration the extended spartan-3a family is programmed by loading configuration data into robust, reprogrammable, static cmos configuration latches (ccl s) that collectively control all functional elements and routing resources. the fpga configuration data is stored ex ternally in a prom or some other nonvolatile medium, either on or off the board, or stored within the fpga in the nonvolatile spartan-3an devices. after applying power, the configuration data is written to the fpga using any of eight different modes: ? master serial from a xilinx platform flash prom ? serial peripheral interface (spi) from an industry- standard spi serial flash ? internal spi flash memory (spartan-3an devices) ? byte peripheral interface (bpi) up from an industry- standard x8 or x8/x16 parallel nor flash ? slave serial, typically downloaded from a processor ? slave parallel, typically downloaded from a processor ? boundary scan (jtag), typically downloaded from a processor or system tester ? multiboot configuration multiboot configuration allows two or more fpga configuration bitstreams to be stored in a single spi serial flash or a parallel nor flash. the fpga application controls which configuration to load next and when to load it. additionally, each fpga in the extended spartan-3a family contains a unique, factory-programmed device dna identifier useful for tracking purposes, anti-cloning designs, or ip protection. i/o capabilities the selectio interface of the extended spartan-3a family supports many popular single-ended and differential standards. ta b l e 2 shows the maximum number of user i/os and input-only pins for each device/package combination. fpgas in the extended spartan-3a family support the following single-ended standards: ? 3.3v low-voltage ttl (lvttl) ? low-voltage cmos (lvcmos) at 3.3v, 2.5v, 1.8v, 1.5v, or 1.2v ? 3.3v pci at 33 mhz or 66 mhz ? hstl i, ii, and iii at 1.5v and 1.8v, commonly used in memory applications ? sstl i and ii at 1.8v, 2.5v, and 3.3v, commonly used for memory applications fpgas in the extended spartan-3a family support the following differential standards: ? lvds, mini-lvds, rsds, and ppds i/o at 2.5v or 3.3v ? bus lvds i/o at 2.5v ? tmds i/o at 3.3v ? differential hstl and sstl i/o ? lvpecl inputs at 2.5v or 3.3v
extended spartan-3a family overview ds706 (v1.1) february 2, 2011 www.xilinx.com product specification 4 r package marking figure 1 provides a top marking example for the extended spartan-3a family in the quad-flat packages. figure 2 shows the top marking for the extended spartan-3a family in bga packages. the markings for the bga packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball a1 indicator. the ?5c? and ?4i? speed grade/temperature range part combinations might be dual marked as ?5c/4i?. ta bl e 2 : available user i/os device vq100 vqg100 tq144 tqg144 ft256 ftg256 fg320 fgg320 fg400 fgg400 cs484 csg484 fg484 fgg484 fg676 fgg676 body size (mm) 14x14 ( 1 ) 20x20 ( 1 ) 17 x 17 19 x 19 21 x 21 19 x 19 23 x 23 27 x 27 xc3s50a/an 68 ( 2 ) 108144 - - - - - xc3s200a/an 68 ( 2 ) - 195 248 ( 2 ) - - - - xc3s400a/an - - 195 251 ( 2 ) 311 - - - xc3s700a/an - - 161 ( 2 ) - 311 ( 2 ) -372 - xc3s1400a/an - - 161 ( 2 ) - - -375502 xc3sd1800a - ----309-519 XC3SD3400A - ----309-469 notes: 1. the footprints for the vq/tq packages are larger than the package body. see the package drawings ( http://www.xilinx.com/support/documentation/package_specifications.htm ) for details. 2. these options are available only in the spartan-3a devices, not the spartan-3an devices. see the data sheets for each device for pb and pb-free package option availability. x-ref target - figure 1 figure 1: extended spartan-3a device qfp package marking example x-ref target - figure 2 figure 2: extended spartan-3a device bga package marking example d a te code m as k revi s ion code proce ss technology xc 3s 50a tm tq144agq0625 d12 3 4567a 4c spartan device type p a ck a ge s peed gr a de temper a t u re r a nge f ab ric a tion code pin p1 r r d s 706_01_07250 8 lot code lot code d a te code xc 3s 50a tm 4c spartan device type bga b a ll a1 p a ck a ge s peed gr a de temper a t u re r a nge r r d s 706_02_07250 8 ft256 a gq0625 d12 3 4567a m as k revi s ion code proce ss code f ab ric a tion code
extended spartan-3a family overview ds706 (v1.1) february 2, 2011 www.xilinx.com product specification 5 r ordering information the extended spartan-3a family is available in both standard and pb-free packaging options for all options of the spartan-3a devices and the spartan-3a dsp devices, and for most options of the spartan-3an devices (see ds557 , spartan-3an fpga family: introduction and ordering information for details).the pb-free packages include a ?g? character in the ordering code (see figure 3 ). x-ref target - figure 3 figure 3: ordering information xc 3s 50a -4 ftg256 c device type s peed gr a de temper a t u re r a nge p a ck a ge type/n u m b er of pin s example: d s 706_0 3 _07250 8 device speed grade package type / number of pins temperature range (t j ) xc3s50a/an ?4 standard performance vq(g)100 100-pin very thin quad flat pack (vqfp) c commercial (0c to 85c) xc3s200a/an ?5 high performance tq(g)144 144-pin thin q uad flat pack (tqfp) i industrial (?40c to 100c) xc3s400a/an ft(g)256 256-ball fine-pitc h thin ball grid array (ftbga) li low power industrial (?40c to 100c) for spartan-3a dsp devices (see ds610 , spartan-3a dsp fpga data sheet ) xc3s700a/an fg(g)320 320-ball fine- pitch ball grid array (fbga) xc3s1400a/an fg(g)400 400-ball fine- pitch ball grid array (fbga) xc3sd1800a cs(g)484 484-ball chip-scale ball grid array (fbga) XC3SD3400A fg(g)484 484- ball fine-pitch ball grid array (fbga) fg(g)676 676-ball fi ne-pitch ball grid array (fbga) notes: 1. the ?5 speed grade is exclusively available in the commercial temperature range.
extended spartan-3a family overview ds706 (v1.1) february 2, 2011 www.xilinx.com product specification 6 r extended spartan-3a family documentation complete and up-to-date documentation of the extended spartan-3a family of fpgas is available on the xilinx website. the following files are also available for download: ds529 , spartan-3a fpga data sheet ds610 , spartan-3a dsp fpga data sheet ds557 , spartan-3an fpga data sheet these data sheets contain dc and switching characteristic specifications and pinouts for the extended spartan-3a family. ug331 , spartan-3 generation fpga user guide this guide includes chapters on: ? clocking resources ? digital clock managers (dcms) ? block ram ? configurable logic blocks (clbs) ? i/o resources ? embedded multiplier blocks ? programmable interconnect ?ise design tools ?ip cores ? embedded processing and control solutions ? pin types and package overview ? package drawings ? powering fpgas ? power management ug332 , spartan-3 generation configuration user guide this guide includes chapters on: ? configuration overview ? detailed descriptions by mode ? ise impact programming examples ? multiboot reconfiguration ? design authentication using device dna ug333 , spartan-3an fpga in-system flash user guide this guide provides information for spartan-3an fpga applications that write to or read from the in-system flash memory after configuration: ? spi_access interface ? in-system flash memory architecture ? read, program, and erase commands ? status registers ? sector protection and sector lockdown features ? security register with unique identifier ug431 , xtremedsp dsp48a for spartan-3a dsp fpgas user guide this guide describes the dsp48a slices and the dsp48a pre-adder. extended spartan-3a family starter kits for specific hardware examples, see the starter kit boards for the extended spartan-3a family. the following web page has links to various boards for each family, including design examples and the user guides: http://www.xilinx.com/product s/boards/s3_sk_promo.htm revision history the following table shows the revision history for this document: date version description of revisions 08/04/08 1.0 initial xilinx release. 01/29/10 1.0.1 corrected typo in the slice count for xc3sd1800a in ta b l e 1 . 02/02/11 1.1 updated for new spartan-3an family par t/package combinations: xc3s50an and xc3s400an in ft(g)256 package, and xc3s1400an in fg(g)484 package. removed footnote for maximum user i/o for xc3s50a/an in ta b l e 1 . updated ta b l e 2 content and table notes. updated device temperature table.
extended spartan-3a family overview ds706 (v1.1) february 2, 2011 www.xilinx.com product specification 7 r notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein (?products?) are subject to the terms and conditions of the xilinx limite d warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated in the xilinx data sheet. all specifications are subject to change without notice. products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance, such as life-support or safety devic es or systems, or any other application that invokes the potential risks of death, personal injury, or property or environmental damage (?critical applications?). use of products in critical applications is at the sole risk of customer, subject to applicable laws and regulations.
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